Architectures of Wireless Transceivers

Architectures of Wireless Transceivers

In year of 2008 I composed a new lecture which addresses the difficult trade of between advanced algorithm design for communication systems and the field of hardware design for mobile devices. The lecture ‘Architectures of Wireless Transceivers’ was given in the winter term 2011-2012 at Karlsruhe Institute of Technology (KIT) and will be given this summer term 2012 at the University of Kaiserslautern.

Description:

The lecture ‘architectures for wireless receivers’ addresses students in electrical engineering, computer engineering and computer science who are interested in the field of communications engineering, architectures and microelectronic design. Special focus is put on implementation aspects and implementation constraints of modern channel coding techniques, which are utilized in current standards like UMTS, LTE, WiMAX and DVB-S2, DVB-T2, DVB-C2. A joint understanding of communication algorithms and implementation constraints is mandatory to obtain an efficient decoder design. A new trend of architecture constraint algorithm design has already entered communication standards committees. E.g., in the LTE standard, where algorithmic parts were introduced with an efficient implementation strategy in mind. The difficult trade off between the hardware world and the communications world is shown. The history of VLSI design and its expected trends will be presented. The microelectronic constraints are then linked to wireless communication standards and their evolving throughput and flexibility requirements. Flexibility demands raise the question: why don’t we just use a general purpose processor in a base station or in a mobile device? One of the most important building blocks for dedicated hardware design is the static random access memory (SRAM). We will revise this component from a high level design perspective. Major focus lies on the power consumption, area and access patterns. How can the power consumption be calculated utilizing a memory explorer? How does the power consumption change when increasing the throughput requirements? Metrics are necessary to evaluate resulting hardware architectures. How is the complexity linked to different algorithmic realizations? Is the number of operations in a Matlab-implementation the right metric to choose among different algorithms? How can appropriate architectural metrics be linked with metrics for the quality-of-service defined in communication systems? To show the problems that arise during hardware, refined design steps of industrial decoder IP cores are shown. Turbo codes and low-density parity-check codes are among the most advanced channel coding schemes. Currently they are utilized in modern communication standards like the 3rd generation mobile standard or the second generation of digital video broadcasting (DVB-S2). Design examples as well as algorithmic techniques for an efficient design are presented.